Bus architecture comparison: Intel Ivybridge bus controller system and Sega architectures

Intel bus interface

Intel buses:

Modern Intel CPUs utilize several buses to facilitate communication between different components. 

These include the 

front-side bus (FSB)

back-side bus (BSB)

Ring Bus.

Intel motherboard: Northbridge, GPU, Serial Bus

Front-Side Bus (FSB):

Connects the CPU to the northbridge (and subsequently the southbridge) of the chipset. 

The FSB connects the CPU to the northbridge, while the BSB connects the CPU to the L2 cache. The ring bus, introduced more recently by Intel, acts as a high-speed interconnect between CPU cores, integrated graphics, and the system agent. 

Historically used to connect the CPU to the rest of the system, including memory and other peripherals. 

Has been replaced by more modern architectures like the ring bus since 2013. 

Back-Side Bus (BSB):

Connects the CPU to the L2 cache (often off-die in older architectures).

Used in conjunction with an FSB in a dual-bus architecture (Dual Independent Bus or DIB).

Became less prominent as on-die L2 cache became standard. 

Ring Bus:

Introduced by Intel as a high-speed interconnect on multi-core processors.

Connects CPU cores, integrated graphics (IGP), L3 cache, and the system agent.

Provides a circular data path for efficient communication between these components.

Data travels along the shortest physical path, minimizing latency.

Composed of four rings: data, request, acknowledge, and snoop.

Scales bandwidth with the number of cores. 

Other Buses:

Besides the FSB, BSB, and Ring bus, Intel CPUs also utilize other buses for specific purposes, such as the data bus, address bus, and control bus for communication with main memory (RAM). 

The PCI bus, AGP bus, and memory buses also connect to the chipset to allow data to flow between connected devices. New serial interfaces included PCIe (express) for additional bandwidth.

In summary, Intel CPUs employ various buses to facilitate communication between different components. The FSB, BSB, and ring bus are crucial for connecting the CPU to the rest of the system and its internal components, while other buses handle specific data transfer tasks. 

SEGA serial interfaces

Mega Drive and Mega CD bus arbiter:

The Mega CD (Sega CD in North America) uses a bus arbiter to manage access to the shared memory and peripherals when both the main Mega Drive (Genesis) CPU and the Mega CD's co-processor are operating simultaneously. This ensures that only one processor can access the shared bus at any given time, preventing data conflicts and ensuring proper operation. 

Here's a more detailed explanation: 

Multi-master Bus System:

The Mega Drive and Mega CD share a common bus, meaning both processors could potentially try to access the same memory or peripherals at the same time. This technique also used for parralel supescalar processing on multi 68k cpu boards to replace Intel controllers for parallel processing.

Bus Arbiter's Role:

A bus arbiter is a dedicated component that acts as a traffic controller for the bus. It decides which processor gets to use the bus at any given moment.

Avoiding Conflicts:

By arbitrating access, the bus arbiter prevents both processors from trying to write to the same memory location or perform conflicting operations simultaneously, which could lead to crashes or data corruption using interleaving for requests to evenly stagger memory access transfers.

Potential Performance Impact:

While the bus arbiter is essential for correct operation, it can also introduce a slight performance overhead if not managed efficiently. Games need to be programmed carefully to minimize the time the processors are stalled waiting for bus access.

Example of Shared Resource:

A good example of where the bus arbiter is needed is when the Mega CD is loading data from the CD-ROM into the Mega Drive's RAM. The Mega CD would request the bus, and the arbiter would grant it access, allowing the data transfer to occur.

Saturn MCU (Master Control Unit):

Sega Saturn used a memory controller and dma system based on their experience with Hitachi bus controllers to achieve parallel processing and memory transfer over a unified memory map, allowing all cpus, memory bank and ic's to operate more or less concurrently and independently for true parallelism across all components at high bandwidth. The MCU could also be programmed using Assembly with a 32bit 35Mhz dsp for co-processing as well as the DMA unit streamlining memory operations.

Dreamcast Maple Bus:

Sega's Sega Block memory unit uses Sega's Maple protocol to connect GD-Rom, Modem / External device and peripheral with the gpu in a 32bit data line which connect all systems into one unit.

This allows arbitration of data moving through the system to be sorted in one place and the system and video memory are divided into 2 chips, each with 32bit width and symmetric bi-directional data lines for efficient movement of data in and out of memory addresses on the system address external bus line or fsb front serial bus.

Maple uses a usb-like interface protocol for connecting multiple devices such as pointing devices, mouse and keyboard or gyroscopic peripherals such as Wii Fit boards and Wii mote.

Dreamcast Maple serial interface uses a 32bit wide bus

The technology and modular concept of rumble packs and expansion memory blocks later saw use in the Wii game console. Although the Wii contained 512MB of data storage, internally. The Wii-mote could be fitted with additional control devices such as steering wheel or gun handle and trigger.

The Maple unified serial bus achieves parallel processing and wide bandwidth to all parts of the system and was developed independently of USB, which released around the same time and Intel's Ring system interface is still lower bandwidth and without concurrent memory read/write operations [citation needed].